All high-speed parallel buses should be exposed on a single row of pins. If that means DDR chips come in a comically long TSSOP-512 instead of BGA, so be it.
@emily I'm gonna take that and run with it to ALL IC's in through-hole DIP packages, become they remind me of friendly little caterpillars.
The social network of the future: No ads, no corporate surveillance, ethical design, and decentralization! Own your data with Mastodon!